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MC74HC161A, MC74HC163A Presettable Counters
High-Performance Silicon-Gate CMOS
The MC74HC161A and HC163A are identical in pinout to the LS161 and LS163. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC161A and HC163A are programmable 4-bit binary counters with asynchronous and synchronous reset, respectively.
Features
16 1
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16 PDIP-16 N SUFFIX CASE 648 1 16 16 1 SOIC-16 D SUFFIX CASE 751B 1 HC16xAG AWLYWW MC74HC16xAN AWLYYWWG
* * * * * * * *
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 192 FETs or 48 Equivalent Gates Pb-Free Packages are Available*
16 16 1 SOEIAJ-16 F SUFFIX CASE 966 1 74HC16xA ALYW
16 16 1 TSSOP-16 DT SUFFIX CASE 948F 1 x A WL, L Y, YY W, WW G = 1 or 3 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package HC 161A ALYW
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
June, 2006 - Rev. 11
1
Publication Order Number: MC74HC161A/D
MC74HC161A, MC74HC163A
RESET CLOCK P0 P1 P2 P3 ENABLE P GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RIPPLE CARRY OUT Q0 Q1 Q2 Q3 ENABLE T LOAD
FUNCTION TABLE
Inputs Clock Reset* L H H H H Load X L H H H Enable P Enable T X X H L X X X H X L Output Q Reset Load Preset Data Count No Count No Count
*HC163A only. HC161A is an Asynchronous Reset Device H = high level, L = low level, X = don't care
Figure 1. Pin Assignment
P0 PRESET DATA INPUTS P1 P2 P3 CLOCK
3 4 5 6 2
14 13 12 11 15
Q0 Q1 Q2 Q3 RIPPLE CARRY OUT BCD OR BINARY OUTPUT
RESET LOAD COUNT ENABLES ENABLE P ENABLE T
1 9 7 10 PIN 16 = VCC PIN 8 = GND
Figure 2. Logic Diagram
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DEVICE/MODE TABLE
Count Mode Binary Binary Device Reset Mode HC161A HC163A Asynchronous Synchronous
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MC74HC161A, MC74HC163A
MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance PDIP SOIC TSSOP PDIP SOIC TSSOP (Note 1) Parameter Value *0.5 to )7.0 *0.5 to VCC )0.5 *0.5 v VO v VCC )0.5 $20 $25 $25 $50 $50 *65 to )150 260 )150 78 112 148 750 500 450 Level 1 Oxygen Index: 30% - 35% Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) UL 94 V-0 @ 0.125 in u2000 u200 u1000 V Unit V V V mA mA mA mA mA _C _C _C _C/W
PD
Power Dissipation in Still Air at 85_C
mW
MSL FR VESD
Moisture Sensitivity Flammability Rating ESD Withstand Voltage
$300 mA Above VCC and Below GND at 85_C (Note 5) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78. Latchup Performance
ILATCHUP
RECOMMENDED OPERATING CONDITIONS
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VCC TA DC Supply Voltage (Referenced to GND) 2.0 0 6.0 V V Vin, Vout tr, tf DC Input Voltage, Output Voltage (Referenced to GND) VCC Operating Temperature, All Package Types Input Rise and Fall Time (Figure 4) *55 0 0 0 0 )125 1000 600 500 400 _C ns VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V 6. Unused inputs may not be left open. All inputs must be tied to a high- or low-logic input voltage level.
Symbol
Parameter
Min
Max
Unit
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7. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
VOH
VOL
VIH
ICC
VIL
Iin
Maximum Quiescent Supply Current
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Vin = VCC or GND Iout = 0 mA
Vin = VCC or GND
Vin = VIH or VIL
Vin = VIH or VIL |Iout| v 20 mA
Vin = VIH or VIL
Vin = VIH or VIL |Iout| v 20 mA
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA
MC74HC161A, MC74HC163A
Test Conditions
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|Iout| v 3.6 mA |Iout| v 4.0 mA |Iout| v 5.2 mA |Iout| v 3.6 mA |Iout| v 4.0 mA |Iout| v 5.2 mA VCC V 6.0 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -55 to 25_C 0.1 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.26 0.26 0.26 2.48 3.98 5.48 4.0 0.1 0.1 0.1 1.9 4.4 5.9 Guaranteed Limit v 85_C 1.0 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.33 0.33 0.33 2.34 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 40 v 125_C 1.0 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 160 0.4 0.4 0.4 0.1 0.1 0.1 2.2 3.7 5.2 1.9 4.4 5.9 Unit mA mA V V V V
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MC74HC161A, MC74HC163A
II I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I II III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIIII II II III IIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II II II II II III I IIIIIII IIIIIIIIIIIIIIIIIIIIIIII II I III IIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I IIII IIIIIIII IIIII I II III IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I II II III III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIIII II I II III I I IIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII II IIII I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIII IIIIIIIIIIIIIIIIIIIIIIII II II III III III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II II II III III III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII II I II III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIIIII II II III II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I I IIIIIIII IIIII I II III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIIII III I II II I II III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol fmax Parameter Figure 4, 10 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - Guaranteed Limit v 85_C 5 12 24 28 - 55 to 25_C 6 15 30 35 v 125_C 4 10 20 24 Unit Maximum Clock Frequency (50% Duty Cycle) (Note 8) MHz tPLH Maximum Propagation Delay, Clock to Q 4, 10 120 75 20 16 145 100 22 18 145 100 20 17 110 60 16 14 160 120 23 20 185 135 25 20 185 135 22 19 150 115 18 15 175 130 20 16 160 135 27 22 185 135 28 24 190 140 26 22 95 40 19 16 10 200 150 28 22 220 150 30 23 220 150 25 21 190 140 20 17 210 160 22 20 200 150 30 25 220 150 35 28 230 155 30 25 110 55 22 19 10 ns tPHL 4, 10 ns tPHL Maximum Propagation Delay, Reset to Q (HC161A Only) 5, 10 ns tPLH Maximum Propagation Delay, Enable T to Ripple Carry Out 6, 10 ns tPHL 6, 10 135 100 18 15 120 75 22 18 145 100 22 20 155 120 22 18 75 30 15 13 10 ns tPLH Maximum Propagation Delay, Clock to Ripple Carry Out 4, 10 ns tPHL 4, 10 ns tPHL Maximum Propagation Delay, Reset to Ripple Carry Out (HC161A Only) 5, 10 ns tTLH, tTHL Maximum Output Transition Time, Any Output 5, 10 ns Cin Maximum Input Capacitance 4, 10 pF 8. Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However, if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable. See Applications information in this data sheet. 9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Gate) (Note 10)
2f
45
pF
10. Used to determine the no-load dynamic power consumption: P D = CPD VCC Semiconductor High-Speed CMOS Data Book (DL129/D).
+ ICC VCC . For load considerations, see the ON
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II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I I I II III II II II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIII II II IIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I II III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIIII II II III IIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II II II II II III I IIIIIII IIIIIIIIIIIIIIIIIIIIIIII II I III IIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I IIII IIIIIIII IIIIIIIIIIIIIIIIIIIIII I III III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I II II III III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIIII II I III III I I IIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIII IIIIIIIIIIIIIIIIIIIIIIII II II III III III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II II II III III III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII II I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIII IIIIIIIIIIIIIIIIIIIIIIII II II III III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I I IIIIIIII IIIIIIIIIIIIIIIIIIIIII I II III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIIII III I II II I II III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol tr, tf trec trec tsu tsu tsu tsu tw tw th th th Maximum Input Rise and Fall Times Minimum Pulse Width, Reset (HC161A Only) Minimum Pulse Width, Clock Minimum Recovery Time, Load Inactive to Clock Minimum Recovery Time, Reset Inactive to Clock (HC161A Only) Minimum Hold Time, Clock to Enable T or Enable P Minimum Hold Time, Clock to Reset (HC163A Only) Minimum Hold Time, Clock to Load or Preset Data Inputs Minimum Setup Time, Enable T or Enable P to Clock Minimum Setup Time, Reset to Clock (HC163A Only) Minimum Setup Time, Load to Clock Minimum Setup Time, Preset Data Inputs to Clock Parameter
MC74HC161A, MC74HC163A
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Figure 5 4 8 5 9 7 8 9 7 8 8 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 1000 800 500 400 60 25 12 10 60 25 12 10 80 35 15 12 80 35 15 12 80 35 20 17 60 25 20 17 60 25 15 12 40 20 15 12 3 3 3 3 3 3 3 3 3 3 3 3 Guaranteed Limit v 85_C 1000 800 500 400 75 30 15 13 75 30 15 13 95 40 20 17 95 40 20 17 95 40 25 23 75 30 25 23 75 30 20 18 60 30 20 18 3 3 3 3 3 3 3 3 3 3 3 3 v 125_C 1000 800 500 400 110 50 26 23 110 50 26 23 110 50 35 25 90 40 18 15 90 40 18 15 90 40 35 25 90 40 30 20 80 40 30 20 3 3 3 3 3 3 3 3 3 3 3 3 Unit ns ns ns ns ns ns ns ns ns ns ns ns
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MC74HC161A, MC74HC163A
FUNCTION DESCRIPTION The HC161A/163A are programmable 4-bit synchronous counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading, and count-enable controls. The HC161A and HC163A are binary counters with asynchronous Reset and synchronous Reset, respectively.
INPUTS Clock (Pin 2) CONTROL FUNCTIONS Resetting
A low level on the Reset pin (Pin 1) resets the internal flip-flops and sets the outputs (Q0 through Q3) to a low level. The HC161A resets asynchronously, and the HC163A resets with the rising edge of the Clock input (synchronous reset).
Loading
The internal flip-flops toggle and the output count advances with the rising edge of the Clock input. In addition, control functions, such as resetting and loading, occur with the rising edge of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
With the rising edge of the Clock, a low level on Load (Pin 9) loads the data from the Preset Data input pins (P0, P1, P2, P3) into the internal flip-flops and onto the output pins, Q0 through Q3. The count function is disabled as long as Load is low.
Count Enable/Disable
These are the data inputs for programmable counting. Data on these pins may be synchronously loaded into the internal flip-flops and appear at the counter outputs. P0 (Pin 3) is the least-significant bit and P3 (Pin 6) is the most-significant bit.
OUTPUTS Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
These devices have two count-enable control pins: Enable P (Pin 7) and Enable T (Pin 10). The devices count when these two pins and the Load pin are high. The logic equation is:
Count Enable = Enable P * Enable T * Load
These are the counter outputs. Q0 (Pin 14) is the least-significant bit and Q3 (Pin 11) is the most-significant bit.
Ripple Carry Out (Pin 15)
The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a count-enable control: Enable T is both a count-enable and a Ripple-Carry Output control.
Table 1. Count Enable/Disable
Control Inputs Load H L X X Enable P H H L X Enable T H H H L Result at Outputs Q0 - Q3 Count No Count No Count No Count Ripple Carry Out High when Q0-Q3 are maximum* High when Q0-Q3 are maximum* L
When the counter is in its maximum state, 1111, this output goes high, providing an external look-ahead carry pulse that may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count state. The logic equation for this output is:
Ripple Carry Out = Enable T * Q0 * Q1 * Q2 * Q3
OUTPUT STATE DIAGRAMS
0 1 2 3 4
*Q0 through Q3 are maximum when Q3, Q2, Q1, Q0 = 1111.
15
5
14
6
13
7
12
11
10
9
8
Figure 3. Binary Counters
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MC74HC161A, MC74HC163A
SWITCHING WAVEFORMS
tr CLOCK 90% 50% 10% tw 1/fmax tPLH tPHL ANY OUTPUT CLOCK tf tw RESET tPHL 50% trec 50% 50%
VCC GND
VCC GND
ANY OUTPUT
90% 50% 10%
VCC GND
tTLH
tTHL
Figure 4.
Figure 5.
tr ENABLE T tPLH RIPPLE CARRY OUT 90% 50% 10% 90% 50% 10%
tf
VCC GND tPHL
RESET tsu CLOCK
50% th VCC 50% GND
tTLH
tTHL
Figure 6.
Figure 7. HC163A Only
VALID INPUTS P0, P1, P2, P3 50% tsu LOAD 50% tsu CLOCK th 50% trec VCC GND th VCC GND VCC GND ENABLE T OR ENABLE P 50% tsu th 50% VALID VCC GND VCC GND
CLOCK
Figure 8.
Figure 9.
TEST CIRCUIT
TEST POINT OUTPUT DEVICE UNDER TEST CL*
*Includes all probe and jig capacitance
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8
14 Q0
P0
3
T0 R Q0 C C LOAD LOAD Q0 P0
13
Q1
P1 4
T1 Q1 R C C LOAD LOAD Q1 P1
12
Q2
P2
5
T2 R Q2 C C LOAD LOAD Q2 P2
MC74HC161A, MC74HC163A
Figure 11. 4-Bit Binary Counter with Asynchronous Reset (MC74HC161A)
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T3 R Q3 C C LOAD LOAD P3 R LOAD LOAD C C
9
11
Q3
P3
6
ENABLE P
7 VCC= PIN 16 GND = PIN 8
15 RIPPLE CARRY OUT
ENABLE T
10
RESET
1
LOAD
9
CLOCK
2
The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle- Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low.
MC74HC161A, MC74HC163A
Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one and two. 4. Inhibit. RESET (HC161A) RESET (HC163A) LOAD
(ASYNCHRONOUS) (SYNCHRONOUS)
P0 PRESET DATA INPUTS P1 P2 P3 CLOCK (HC161A) CLOCK (HC163A)
COUNT ENABLES
ENABLE P ENABLE T Q0 Q1
OUTPUTS Q2 Q3 RIPPLE CARRY OUT RESET
12 LOAD
13 14
15
0
1
2 INHIBIT
COUNT
Figure 12. Timing Diagram
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14 Q0
P0
3
T0 R Q0 C C LOAD LOAD Q0 P0
13
Q1
P1
4
T1 Q1 R C C LOAD LOAD Q1 P1
12
Q2
P2
5
T2 R Q2 C C LOAD LOAD Q2 P2
MC74HC161A, MC74HC163A
Figure 13. 4-Bit Binary Counter with Synchronous Reset (MC74HC163A)
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T3 R Q3 C C LOAD LOAD P3 R LOAD LOAD C C
11
11
Q3
P3
6
ENABLE P
7 VCC= PIN 16 GND = PIN 8
15 RIPPLE CARRY OUT
ENABLE T
10
RESET
1
LOAD
9
CLOCK
2
The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle- Enable flip-flop is a combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to the Q output of the flip-flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-flop low.
MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS CASCADING
LOAD INPUTS INPUTS INPUTS
LOAD P0 P1 P2 P3 H = COUNT L = DISABLE H = COUNT L = DISABLE ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK R RESET OUTPUTS CLOCK Q0 Q1 Q2 Q3
LOAD P0 P1 P2 P3 ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK R Q0 Q1 Q2 Q3
LOAD P0 P1 P2 P3 ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK R Q0 Q1 Q2 Q3 TO MORE SIGNIFICANT STAGES
OUTPUTS
OUTPUTS
NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and Clock.
Figure 14. N-Bit Synchronous Counters
INPUTS LOAD ENABLE P ENABLE T LOAD P0 P1 P2 P3 ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK CLOCK R RESET Q0 Q1 Q2 Q3
INPUTS
INPUTS
LOAD P0 P1 P2 P3 ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK R Q0 Q1 Q2 Q3
LOAD P0 P1 P2 P3 ENABLE P RIPPLE ENABLE T CARRY OUT CLOCK R Q0 Q1 Q2 Q3 TO MORE SIGNIFICANT STAGES
OUTPUTS
OUTPUTS
OUTPUTS
Figure 15. Nibble Ripple Counter http://onsemi.com
12
MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS VARYING THE MODULUS
HC163A OTHER Q0 INPUTS Q1 Q2 Q3 RESET OPTIONAL BUFFER FOR NOISE REJECTION OUTPUT
HC163A OTHER Q0 INPUTS Q1 Q2 Q3 RESET OPTIONAL BUFFER FOR NOISE REJECTION OUTPUT
Figure 16. Modulo-5 Counter
Figure 17. Modulo-11 Counter
The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitch-free due to the synchronous Reset.
ORDERING INFORMATION
Device MC74HC161AN MC74HC161ANG MC74HC161AD MC74HC161ADG MC74HC161ADR2 MC74HC161ADR2G MC74HC161AFEL MC74HC161ADTR2 MC74HC163AN MC74HC163ANG MC74HC163AD MC74HC163ADG MC74HC4163DR2 MC74HC163ADR2G MC74HC163AFEL Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOEIAJ-16 TSSOP-16* PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOEIAJ-16 Shipping 500 Units / Box 500 Units / Box 48 Units / Rail 48 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 2000 Units / Tape & Reel 2500 Units / Tape & Reel 500 Units / Box 500 Units / Box 48 Units / Rail 48 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 2000 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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13
MC74HC161A, MC74HC163A
PACKAGE DIMENSIONS
PDIP-16 N SUFFIX CASE 648-08 ISSUE T
-A-
16 9
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
F S
C
L
-T- H K G D
16 PL
SEATING PLANE
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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14
MC74HC161A, MC74HC163A
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z
D A VIEW P c
e
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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15
MC74HC161A, MC74HC163A
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
16 9
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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16
CCC EEE CCC EEE CCC
K1
SECTION N-N
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74HC161A/D

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